The present invention relates to a cache control device and a cache control method, and for example, a cache control device and a cache control method, which divide an area of a cache memory.
Parallel processing of a multiprocessor or a multithread, or a cache of instructions or data is suited for a solution to performance degradation attributable to a speed difference between a processor and a memory. Also, in the parallel processing under a real-time control, a property that a fluctuation of a processing time caused by an inter-task interference is reduced, and specific processing can be completed within a given real time is required.
Japanese Unexamined Patent Application Publication No. 2010-86128 discloses a technique related to a multithread processor for enabling a hardware thread to be flexibly selected while ensuring a minimum execution time of the hardware thread. A thread scheduler provided in the multithread processor disclosed in Japanese Unexamined Patent Application Publication No. 2010-86128 designates the execution of at least one hardware thread fixedly selected in a predetermined first execution time, and designates the execution of an arbitrary hardware thread in a second execution time.
In this example, in the processor having the cache, there occurs a variation in cache hit ratio caused by such an interference that a cache area for one task is overwritten for another task. Under the circumstances, Japanese Unexamined Patent Application Publication No. 2004-178571 discloses a technique in which the area of the cache memory is divided, and allocated to a plurality of tasks, individually. A cache control device disclosed in Japanese Unexamined Patent Application Publication No. 2004-178571 includes an area management unit that manages the respective tasks which are processed in parallel by a microprocessor, in association with the respective areas into which the memory area of the cache memory is divided. That is, in Japanese Unexamined Patent Application Publication No. 2004-178571, the cache memory areas that can be operated by the respective tasks are restricted to solve the interference between the tasks. Also, Japanese Unexamined Patent Application Publication Nos. Hei-07 (1995)-248967, 2005-071046, and 2001-109661 disclose a technique in which a capacity of the cache memory is allocated on the basis of a priority of the tasks (or processes).